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MAX823SEXK Rev. A
RELIABILITY REPORT FOR MAX823SEXK PLASTIC ENCAPSULATED DEVICES
August 2, 2003
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX823S successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information IV. .......Die Information V. ........Quality Assurance Information VI. .......Reliability Evaluation ......Attachments
I. Device Description A. General The MAX823S microprocessor (P) supervisory circuit combines reset output, watchdog, and manual reset input functions in 5-pin SOT23 and SC70 packages. It significantly improve system reliability and accuracy compared to separate ICs or discrete components. The MAX823S is specifically designed to ignore fast transients on VCC. The MAX823S has a eset threshold voltage of 2.93V. The device has an active-low reset output, which is guaranteed to be in the correct state for VCC down to 1V. The MAX823 offers a watchdog input and manual reset input. . B. Absolute Maximum Ratings Item VCC All Other Pins Input Current, All Pins Except RESET and RESET Output Current, RESET, RESET Operating Temperature Range MAX823SEXK. MAX823SEUK Storage Temperature Range Lead Temperature (soldering, 10s) Continuous Power Dissipation (TA = +70C) 5-Pin SOT23 5-Pin SC70 Derates above +70C 5-Pin SOT23 5-Pin SC70 Rating -0.3V to +6.0V -0.3V to (VCC + 0.3V) 20mA 20mA -40C to +85C -40C to +125C -65C to +150C +300C 571mW 247mW 7.1mW/C 3.1mW/C
II. Manufacturing Information A. Description/Function: 5-Pin Microprocessor Supervisory Circuits With Watchdog Timer and Manual Reset B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: B12 (Standard 1.2 micron silicon gate CMOS) 607 California, USA Malaysia or Thailand January, 1997
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard JESD22-112: 5-Lead SOT23 Copper Solder Plate Silver-Filled Epoxy Gold (1.0 mil dia.) Epoxy with silica filler Buildsheet # 05-1601-0010 Class UL94-V0 5-Lead SC70 Alloy 42 Solder Plate Non-Conductive Epoxy Gold (1.0 mil dia.) Epoxy with silica filler Buildsheet # 05-1601-0111 Class UL94-V0
Level 1
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 42 x 36 mils Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) Aluminum/Si (Si = 1%) None 1.2 microns (as drawn) 1.2 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Manager, Reliability Operations) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 135C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 (Chi square value for MTTF upper limit) 192 x 4389 x 320 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV = 3.39 x 10-9 = 3.39 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-5033) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The MS04-3 die type has been found to have all pins able to withstand a transient pulse of 1500V per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 250mA.
Table 1 Reliability Evaluation Test Results MAX823SEXK TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
PACKAGE
Static Life Test (Note 1) Ta = 135C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
320
0
DC Parameters & functionality
SOT23 SC70
77 77
0 0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters & functionality 77 0
Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Package/Process data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., V , or V SS1 SS2 or V SS3 or V CC1 , or V CC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
TERMINAL D Mil Std 883D Method 3015.7 Notice 8
ONCE PER SOCKET
ONCE PER BOARD
100 OHMS
+5V 700uA
1 2 3 4
8 7 6 5
0.1uF
8-DIP
DEVICES: MAX 941/809/810/823/824/825/803 MAX 6381/6835 MAX. EXPECTED CURRENT = 700uA AND 15uA
DOCUMENT I.D. 06-5033 REVISION E
DRAWN BY: HAK TAN NOTES: 15 uA FOR MAX 6381
MAXIM TITLE: BI Circuit (MAX 6381/803/809/810/823/824/825/941/6835)
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